1. Technical Field
The present invention relates in general to semiconductor circuit design and, in particular, to a system and method for optimizing the yield of circuits produced from a semiconductor wafer. Still more particularly, the present invention relates to a system and method for optimizing the yield of circuits produced from a semiconductor wafer by requiring minimum design rules to be exceeded a particular percentage of occasions within the layout of the circuit.
2. Description of the Related Art
Fabrication of semiconductor integrated circuits (IC""s) is an extremely complex process that involves several hundred or more operations. They are fabricated by the use of photo-lithographic processes, in which complex shape patterns are transferred from a masking structure, i.e. a mask, into a photosensitive material, typically photo resist, which is deposited onto the surface of a silicon wafer. The mask image is transferred into the resist by exposing the masked photo resist to light, and then xe2x80x9cdevelopingxe2x80x9d the resist layer to selectively remove the resist in regions exposed to light.
The image thus transferred into the resist can then be used to locally alter the electrical characteristics of the silicon wafer, i.e. by use as selective blocking layers for ion implantation. Another use of the masking process is for the selective removal of regions in layers of conductive and insulating materials which are deposited sequentially on the silicon wafer. These processes are used to define wiring layers and interconnects between wiring layers in the IC""s produced.
Semiconductor IC""s are not manufactured individually, but rather as an assembly of many chips on a wafer which is then diced up to produce the individual chips.
Increasing production yield is an ongoing challenge in the manufacture of semiconductor chips. Because of various defects that can occur in the fabrication of a wafer, significant numbers of wafer die have to be discarded for one reason or another, thereby decreasing the percentage yield per wafer and driving up the cost of individual chips. Defects are typically caused by foreign particles, minute scratches, and other imperfections introduced during photo-resist, photo-mask, etching, and diffusion operations. Yield loss increases the number of wafer starts at the inception of production needed to meet specific customer order quantities for finished chips at the end of the production line and limits the number of good parts which can be sold.
Virtually all complex integrated circuits are designed with the use of computer aided design tools. Some CAD tools, called simulators, help the circuit designer verify the operation of a proposed circuit. Another type of CAD tool is used for automatic layout. This tool generates the shape patterns used to produce photo masks from a detailed circuit specification. These shape patterns used to produce a set of masks for a particular circuit are commonly called the circuit layout. Other types of circuit layout may be generated manually by a mask layout technician using graphical editing tools.
Circuit layouts are usually comprised of shapes drawn on multiple mask levels and are used to determine the presence of various materials in the semiconductor IC production. For instance, some layers of the circuit layout will define the regions of the semiconductor substrate that are doped with n-type or p-type dopants, while other layers of the circuit layout will define regions in which materials are deposited on the top of the substrate, such as polysilicon or metal regions, while yet other layers will define apertures to be formed in various layers of material so as to form connections between layers of the semiconductor circuit. Each layer of a circuit layout is defined as a set of polygons, or cells.
FIG. 1 illustrates an idealized simple layout of a conventional integrated circuit design 10 that includes logic circuits and conductive lines in accordance with the prior art. A region of interest 11 has a conductive line 12, which provides an input signal xe2x80x9cAxe2x80x9d to circuits 16 and 18 that generate output signals xe2x80x9cCxe2x80x9d and xe2x80x9cDxe2x80x9d, which are transmitted through conductive lines 22 and 24, respectively. Similarly, region 11 includes another conductive line 14, which provides another input signal xe2x80x9cBxe2x80x9d to circuit 20 that generates an output signal xe2x80x9cExe2x80x9d, which is transmitted through conductive line 26. It should be noted that some or all of the elements of the logic circuits may exist at layers other than the layer on which the conductive lines exist. Conductive line 26 is close enough to conductive line 24 to form an area that is sensitive to a particle, such as particle 28, which is present in this area and in physical contact with conductive lines 26 and 24 and may short-circuit output signals D and E.
The layout design of IC devices, such as metal oxide semiconductor (MOS) transistors, and circuits is constrained by a set of rules called the xe2x80x9cminimum design rulesxe2x80x9d or xe2x80x9cground rulesxe2x80x9d. These rules typically represent the photo-lithographic and process limits of resolution for a given xe2x80x9ctechnologyxe2x80x9d. The rules generally specify minimum sizes, spaces, and overlaps allowed, for and between the various mask layers used in the ultimate production of the semiconductor IC""s. Processes are typically designed on the basis of the minimum feature size and space that can be reliably produced for a given mask level.
While design processes for automatic placement of conductive lines provide a minimum separation distance, they do not account for the general need to arrange the conductive lines in such a manner so that the areas which are especially susceptible to defects are minimized. The design rules that dictate the conventional IC layout, are partly guided by the criteria of minimizing overall chip size and maximizing performance. Because the minimum design rules do not account for areas which are especially susceptible to defects, the yield of usable devices produced from a wafer is not maximized.
Further, circuit layouts which are generated manually often may not be optimized for best yield.
Therefore, a need exists for a method and system for improving a number of usable circuits produced from a semiconductor wafer without increasing the area of the circuit or impacting its performance.
A method and system are disclosed for improving a yield of circuits produced from a semiconductor wafer. A plurality of design rules are established for designing a layout of the circuit within the wafer. A yield-limiting set of the plurality of design rules are selected. Adherence to each of the set of rules throughout all of the layout reduces the yield. For each one of the set of rules, a recommended value is determined. A percentage of occasions each one of the set should be exceeded within the layout is also determined. The layout is then designed so that each one of the set of the plurality of design rules meets or exceeds the recommended value more often than the percentage.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.